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UL62H256A
Low Voltage Automotive Fast 32K x 8 SRAM
Features
! 32768 x 8 bit static CMOS RAM ! 35 and 55 ns Access Time ! Common data inputs and
Description go High-Z until the new information is available. The data outputs have no preferred state. The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively. Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required.
The UL62H256A is a static RAM manufactured using a CMOS process technology with the following operating modes: data outputs - Read - Standby ! Three-state outputs - Write - Data Retention ! Typ. operating supply current The memory array is based on a 35 ns: 45 mA 6-Transistor cell. 55 ns: 30 mA ! Standby current < 40 A at 125 C The circuit is activated by the falling edge of E. The address and ! TTL/CMOS-compatible control inputs open simultaneously. ! Power supply voltage 2.5 - 3.6 V According to the information of W ! Operating temperature range -40 C to 85 C and G, the data inputs, or outputs, -40 C to 125 C are active. In a Read cycle, the data outputs are activated by the ! QS 9000 Quality Standard falling edge of G, afterwards the ! ESD protection > 2000 V (MIL STD 883C M3015.7) data word will be available at the outputs DQ0-DQ7. After the ! Latch-up immunity >100 mA address change, the data outputs ! Package: SOP28 (300/330 mil)
Pin Configuration
Pin Description
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Signal Name A0 - A14 DQ0 - DQ7 E G W VCC VSS
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
SOP
21 20 19 18 17 16 15
Top View
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UL62H256A
Block Diagram
A6 A7 A8 A9 A10 A11 A12 A13 A14
Row Address Inputs
Row Decoder
Memory Cell Array 512 Rows x 64 x 8 Columns
Common Data I/O
A0 A1 A2 A3 A4 A5
Column Address Inputs
Column Decoder
DQ0 Sense Amplifier/ Write Control Logic DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
Address Change Detector
Clock Generator
VCC
VSS
E
W
G
Truth Table Operating Mode Standby/not selected Internal Read Read Write
* H or L
E H L L L
W * H H L
G * H L *
DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
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UL62H256A
Characteristics
All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0.2 V and VIH = 2.8 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage.
Absolute Maximum Ratings a Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Output Short-Circuit Current at VCC = 3.3 V and VO = 0 V c
a
Symbol VCC VI VO PD
Min. -0.3 -0.5 -0.5 -40 -40 -65
Max. 4.6 VCC + 0.5
b
Unit V V V W C C mA
VCC + 0.5 b 1 85 125 150 100
K-Type A-Type
Ta Tstg | IOS |
b c
Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 4.6 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended Operating Conditions Power Supply Voltage Input Low Voltage d Input High Voltage
d
Symbol VCC VIL VIH
Conditions
Min. 2.5 -0.3 2.0
Max. 3.6 0.5 VCC + 0.3
Unit V V V
-2 V at Pulse Width 30 ns
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UL62H256A
Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) VCC VIL VIH tcW tcW VCC VE K-Type A-Type VCC VE K-Type A-Type VCC IOH VCC IOL VCC VIH VCC VIL VCC VOH VCC VOL VCC VOH VCC VOL Conditions = = = = = 3.6 V 0.5 V 2.0 V 35 ns 55 ns Min. Max. Unit
90 70
mA mA
Supply Current - Standby Mode (CMOS level)
ICC(SB)
= 3.6 V = VCC - 0.2 V
10 40
A A
Supply Current - Standby Mode (TTL level)
ICC(SB)1
= 3.6 V = 2.0 V 10 20 = 2.5 V = -1.0 mA = 2.5 V = 2.1 mA = 3.6 V = 3.6 V = 3.6 V = 0V = = = = 2.5 V 2.2 V 2.5 V 0.4 V 2.2 0.4 2 -2 -1.0 2.1 mA mA V V A A mA mA
Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current Output High Current Output Low Current Output Leakage Current High at Three-State Outputs Low at Three-State Outputs
VOH VOL IIH IIL IOH IOL
IOHZ IOLZ
= 3.6 V = 3.6 V = 3.6 V = 0V
2 -2
A A
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UL62H256A
Switching Characteristics Read Cycle Read Cycle Time Address Access Time to Data Valid Chip Enable Access Time to Data Valid G LOW to Data Valid E HIGH to Output in High-Z G HIGH to Output in High-Z E LOW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time from Address Change E LOW to Power-Up Time E HIGH to Power-Down Time Symbol Alt. tRC tAA tACE tOE tHZCE tHZOE tLZCE tLZOE tOH tPU tPD IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) 3 0 3 0 35
Min.
35
Max. Min.
55 Unit
Max.
35 35 35 15 12 12
55 55 55 25 15 15 3 0 3 0 55
ns ns ns ns ns ns ns ns ns ns ns
Switching Characteristics Write Cycle Write Cycle Time Write Pulse Width Write Setup Time Address Setup Time Address Valid to End of Write Chip Enable Setup Time Pulse Width Chip Enable to End of Write Data Setup Time Data Hold Time Address Hold from End of Write W LOW to Output in High-Z G HIGH to Output in High-Z W HIGH to Output in Low-Z G LOW to Output in Low-Z
Symbol Alt. tWC tWP tWP tAS tAW tCW tCW tDS tDH tAH tHZWE tHZOE tLZWE tLZOE IEC tcW tw(W) tsu(W) tsu(A)
tsu(A-WH) Min.
35
Max. Min.
55 Unit
Max.
35 20 20 0 25 25 25 15 0 0 15 12 0 0
55 35 35 0 40 40 40 25 0 0 20 15 0 0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) tdis(G) ten(W) ten(G)
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UL62H256A
Data Retention Mode
E - controlled
VCC VCC(DR) 2 V 2.2 V 0V tsu(DR) Data Retention trec 2.2 V E
3.0 V
VCC(DR) - 0.2 V VE(DR) VCC(DR) + 0.3 V Data Retention Characteristics Data Retention Supply Voltage Data Retention Supply Current Symbol Alt. IEC VCC(DR) ICC(DR) VCC(DR) = 2V VE = VCC(DR) - 0.2 V K-Type A-Type See Data Retention Waveforms (above) 0 tcR
Conditions
Min. 2
Typ.
Max.
Unit V
5 20
A A ns ns
Data Retention Setup Time Operating Recovery Time
tCDR tR
tsu(DR) trec
Test Configuration for Functional Check
3.0 V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 VCC
VIH
VIL
Input level according to the relevant test measurement
Simultaneous measurement of all 8 output pins
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
1076
VO
30 pF e E W G VSS 1260
e
In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.
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UL62H256A
Capacitance Input Capacitance Output Capacitance Conditions VCC VI f Ta = 3.3 V = VSS = 1 MHz = 25 C Symbol CI Co Min. Max. 7 7 Unit pF pF
All pins not under test must be connected with ground by capacitors.
Ordering Code Example Type UL62H256A S A 35 Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Access Time 35 = 35 ns 55 = 55 ns Operating Temperature Range K = -40 to 85 C A = -40 to 125 C
f
Package S = SOP28 (300 mil) S2 = SOP28 (330 mil) Type 2
on special request
Device Marking (example) Product specification Assembly location and trace code Internal Code
ZMD UL62H256ASA 35 C 0425 1 ZZ G1
Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package
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UL62H256A
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = V IL, W = VIH)
tcR
Ai DQi
Output Previous Data Valid tv(A)
Address Valid ta(A) Output Data Valid
Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH)
tcR
Ai E G DQi
Output High-Z tPU 50 % tsu(A) ten(E)
Address Valid ta(E) ta(G) ten(G)
tdis(E) tdis(G)
Output Data Valid tPD 50 %
ICC(OP) ICC(SB)
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UL62H256A
Write Cycle1: W-controlled
tcW
Ai E W DQi
Input tdis(W) tsu(A)
Address tsu(E) tsu(A-WH) tw(W) tsu(D) th(D) ten(W) th(A)
Input Data Valid High-Z
DQi
Output
G
Write Cycle 2: E-controlled
tcW
Ai E W DQi
Input tsu(A)
Address Valid tw(E) tsu(W) tsu(D)
ten(E)
th(A)
th(D) Input Data Valid High-Z
tdis(W) tdis(G)
DQi
Output
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.
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UL62H256A
LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
May 07, 2004
Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de

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